1. Field of the Invention
The present invention relates to a device and a method for associating information concerning memory cells in a memory element with an external memory, and in particular to a device and a method for associating fault information in testing the memory element with the external memory and for filing the information in the same.
2. Description of the Related Art
Dynamic semiconductor memories, such as e.g. DRAMs (DRAM=Dynamic Random Access Memory), as a rule have additional, redundant memory cells apart from a number of memory cells in a regular portion which corresponds to the nominal size of the semiconductor memory. Upon manufacture of a semiconductor memory, all memory cells are tested with respect to operability thereof and defective memory cells in the regular portion are replaced by operable redundant memory cells by re-addressing. The replacement of the memory cells as a rule does not take place individually, but by re-addressing of complete rows or columns of a cell matrix. The information concerning the operability of the memory cells is filed or stored in a fault memory.
All DRAMs usual in the market have nominal sizes corresponding to a power of 2. Changing of the address space with equal memory size by changing the number of inputs/outputs or data channels (DQs) in the same relationship is usual in the art. For example, a reduction of the number of address bits by 1 can be obtained by doubling the number of data channels (DQs) . However, if the bit size of a cell field cannot be expressed by a power of 2, operation takes place in an effective address space corresponding to the next higher power of 2. This is as a rule the case, for example, when a memory element is considered inclusive of its redundant elements. Due to the fact that the number of redundant memory cells as a rule is just a few percent of the number of regular memory cells (e.g. approx. 4% in a 32 MB chip), a large part of the effective address space is thus left unused. This is disadvantageous if the aforementioned testing of the operability of all memory cells of a memory element is carried out with test systems as they are usual in the market, making use of a fault memory of a size corresponding to the effective address space. Consequently, there is arising an unnecessarily high fault memory demand.
In the following, a memory element having four regular memory cells and two redundant memory cells is to be assumed as an example, with each of these cells being addressed via an address. Thus, there are in total six addresses necessary. A fault memory employed in the prior art, thus, would have a size with eight memory cells, since eight is the next higher power of two in relation to six. In this case, there are thus two addresses and the associated memory cells in the fault memory not made use of. The number of unused addresses increases dramatically when this simple example is transferred to larger memory elements.